出租/供应安立MP1764AMP1764A误码仪MP1764A

出租/供应安立MP1764A MP1764A误码仪MP1764A/李S
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深圳佳捷伦电子仪器有限公司
联系人：李S/欧阳
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技术指标
·Specifications Operation frequency 0.05 to 12.5 GHz Data input Input waveform NRZ Input voltage 0.25 to 2.0 Vp-p Threshold voltage variable range -3.000to +1.875Vp-p(1 mV steps) Phase margin ≥70ps(typical value at 10 Gb/s PRBS 2^23-1,andan input amplitude of 1 Vp-p) Input sensitivity 50mVp-p(typical value at 10 Gb/s and PRBS2^23-1) Termination 50Ω connected to GND (other than ECL)orto-2V(ECL) Connector APC-3.5 Clock input Input waveform Rectangular wave(<0.5 GHz),rectangularor sine wave(≥0.5GHz),duty factor:50% Input voltage 0.25 to 2.0 Vp-p Input delay variable range -500 to +500ps(1 ps steps) Polarity inversion CLOCK/CLOCK inversion possible Termination 50Ω connected to GND(other than ECL)or -2V(ECL) Connector APC-3.5 Automatic input data threshold/delay searchfunction Provided voltage/delay(vertical/horizontalaxis) Receive pattern Pseudorandom binary sequence pattern(PRBS) Pattern:2^n-1(n:7,9,11,) Mark ratio:1/2,1/4,1/8,0/8(1/2,3/4, 7/8,8/8 are possible with logic inversion.) Number of AND bit shift when setting mark ratio:1,3 bits(selectable byusing DIP switch on rear panel) Data pattern^*1 Data length:2 to 8388608 bits,Pattern reset/preset:ALL/PAGEsekectable Logic inversion Positive or negative Tracking Information of pattern set by the errordetector is went to the pulse pattern generator via GPIB Alternate pattern A/B pattern word length:128 to 4194304 bits(128bits steps),Number of loops:Controlled using external signal Zero substitution pattern Zero bit length:1 to(patternlength



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